This invention relates generally to digital logic circuitry and more particularly, to a CMOS tri-mode input buffer for generating three groups of binary codes in response to an input signal having three different input voltage levels.
As is generally well known in the prior art, tri-level buffer circuitry are typically used in connection with various test logic circuitry for testing a number of different functions within associated parent circuitry, such as on an integrated circuit microprocessor. In order to provide three different logical inputs into the integrated circuit device to be tested, there would be generally required two input test pins or pads. The advantage of tri-level buffers is that input test signals having three different voltage levels can be applied between the circuit ground reference and a single input test pin or pad, thereby saving use of an extra pin on the integrated circuit device.
In logic design, an input signal has commonly two possible logic states or levels. One state is defined as a high or logic "1" state and the second state is defined as a low or logic "0" state. In CMOS logic, the high state is represented by an upper supply potential VDD, which is typically at +5.0 volts, and the low state is represented by a lower supply potential VSS, which is typically at 0 volts. In the case of tri-level buffer circuitry, there is provided a third input state referred to as a "floating input" state wherein the input is left unconnected (open) or connected to a voltage level that is in between the low state and the high state (i.e., VDD/2).